| 摘要 |
A pipelined charge coupled analog to digital converter which provides a plurality of serially arranged pipelined stages that are connected to pass signal and reference charge packets from stage to stage in a serial progression. The pipelined analog to digital converter includes one stage for each bit desired in the output bit stream, and thus, an analog to digital converter providing an n bit digital word corresponding to the input analog signal charge, includes n stages. While the time necessary to perform the analog to digital conversion is the sum of operating times of all the stages, because the converter is pipelined, each successive n bit digital word representing a different successive charge packet is produced succeeding a preceding digital word representing a preceding signal charge packet, by a delay equal to the processing time of only a single stage. Thus, a charge coupled A/D system is provided including a plurality of pipelined stages for performing successive approximations on a reference charge Qr and an input analog signal charge Qs wherein said pipelined stages include charge processing means each coupled only to directly adjacent stages for performing an inequality function to provide a bit string b1 through bn representing a digital representation of said input analog signal charge Qs. |
