| 摘要 |
A buffer (14) can exchange data between a computer (SL) having a plurality of lines (41) and a device (MC). One of these lines (BH, H1, H2), a halt line, can transmit a halt signal when the computer has halted. The buffer (14) includes a plurality of transmitters (44, 46, 50, 60, 74, 76, 80, 82, 96, 98) and a plurality of controlled receivers (66, 68, 70, 72, 84, 86, 100, 102, 108, 110). A halt transmitter (46) is included among the plurality of transmitters. The transmitters are separately connected to predetermined respective ones (LS1a, LSNa, LS1b, LSNb, L51c, LSNc, X1, XN, A1, AN) of the plurality of lines for transmitting their signals to the device (MC). The halt transmitter (46) is connected to the halt line (BH, H1, H2) for transmitting the halt signal to the device (MC). The receivers are connected between the device (MC) and given respective ones of the plurality of lines (LM1b, LMNb, HLX, BC, X1, XN, A1, AN, AN+1, AN+M) for coupling to them signals from the device (MC). Each one of a predetermined set (100, 102) from the plurality of receivers has a receive terminal (H1) commonly connected to the halt line (H1) for enabling operation of this predetermined set (100, 102) in response to the halt signal.
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