Circuit arrangement for inserting bit or clock error bursts of adjustable length into a binary data signal and an associated binary clock

摘要

The invention relates to a circuit arrangement for inserting bit or clock error bursts of adjustable length into a binary data signal (D) generated from an arbitrarily coded digital signal, and an associated binary clock (T). Thus, particular accurately defined falsifications of the binary data signal (D) and of the binary clock (T) can be generated. Four different types of error can be set with the aid of the error switch (FU). Figure 1 shows a block diagram of the circuit arrangement according to the invention. The arbitrarily coded data signal (S) arriving at the receive interface (SSE) from the line (L) leaves the circuit arrangement again as digital signal (S') falsified in a defined manner at the transmit interface (SSS). <IMAGE>