发明名称 PROGRAMMABLE LOGIC ARRAY
摘要 PURPOSE:To simplify the arrangement of a programmable logic array (PLA) and to shorten the design period by constituting the PLA where unit arrays of longitudinal MOSFET arrays are arranged laterally. CONSTITUTION:The 1st MOSFET array 1 consists of a common gate electrode 2 of polysilicon, contact holes 3 and 4, a common source electrode 5 made of a diffused layer, and the drain electrode of one MOSFET constituting the MOSFET array, and the 1st load element 7 consists of a common source electrode 8, the drain electrode 9 of the MOSFET, and a common gate electrode 10 made of polysilicon. Further, the 2nd MOSFET array 11 having the same structure with the 1st MOSFET array 1 and the 2nd load element 15 are arranged longitudinally in order to constitute a unit array, and plural unit arrays are arranged laterally. Consequently, they are arranged nearly without any gap to save the occupation area on an integrated circuit chip, and the positions of a power source line and a clock line are standardized, so wiring among PLAs is facilitated.
申请公布号 JPS6367819(A) 申请公布日期 1988.03.26
申请号 JP19860213141 申请日期 1986.09.09
申请人 NEC CORP 发明人 FURUKI KATSUYA;SUGIYAMA NOBUYUKI;KITAMURA YOSHINARI
分类号 H03K19/177;H01L27/112 主分类号 H03K19/177
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