| 摘要 |
PURPOSE:To narrow an element isolation width and to obtain a miniaturized high capacity by composing a MOS capacity out of a diffusion layer formed on a surface of a semiconductor principle plane including slopes of a Y-shaped groove, an insulating film, and a polycrystalline semiconductor layer formed on said insulating film. CONSTITUTION:Anisotropic etching of Si is performed by using an oxide film 2 formed on a semiconductor substrate as a mask so as to form a taper groove 3. Next, a vertical groove 13 is formed by dry etching. SiO2 is deposited by CVD and an SiO2 film 14 filling the vertical groove 13 is formed thickly by etching-back. By the overall oxidation, an SiO2 film 6 is formed thinly and a masking member 15 is formed of photoresist. This masking member 15 and the oxide film 14 are used as a mask to form a donner ion implantation N diffusion layer 5. A first layer polysilicon 7 is deposited and a CVD SiO2 is deposited in a manner it covers said polysilicon 7, thereby forming an interlaminar insulating film 8. A gate oxide film 9, a polysilicon gate 10, and a source and drain N<+> layer 11 are formed. Thus, a narrow element isolation groove I can be formed and the enhancement of integration of a capacity can be contrived. |
