| 摘要 |
Limit cycles are eliminated in digital filters driven by zero, d.c. and period 2 inputs, by adjusting the filter output in response to the state variables present within the filter. The filter includes a quantizer (201) adapted to provide a fixed length output word p in response to an input y, where p<y<p+k and k is the quantizer step size. The filter is further arranged to form the products axXn and bxXn, where a and b are multiplier coefficients and Xn and Xn-1, the state variables, are once and twice delayed versions of the filter output Xn+1, and to combine the aforesaid products and the filter input Un to yield the value y. In accordance with the invention, the quantizer output is adjusted to p+k, if Xn-1>p+k or Xn-1=p and ¦Xn+Sgn(a)Xn-1¦>/=T or Xn-1=p+k and ¦Xn+Sgn(a)Sn-1¦<T, where T is a fixed threshold value and Sgn(a) is the sign of the multiplier coefficient a. |
