| 摘要 |
PURPOSE:To implement a high speed and high integration density, by approximately equalizing the widths of N<-> and P-channel MOS type transistors, and making the length of the channel of the P-channel MOS type transistor shorter than the length of the channel of the N-channel transistor. CONSTITUTION:Polysilicon or polycide is deposited on the entire surface of a substrate. Thereafter, the deposited layer is patterned in accordance with a desired gate interconnection pattern. Thus a gate electrode layer 28A for an N channel and a gate electrode 28B for a P channel are formed. The widths of the electrode layers 28A and 28B are made equal. Lengths LGN and LGP (LGN > LGP) of the electrodes 28A and 28B are set. With the laminated layers of the electrode layers and an oxide film 24 beneath the layers as masks, selective p-ion implantation is performed. As a result, an effective N-channel length Lneff and a P-channel length Lpeff are obtained, and Lneff > Lpeff is obtained. In this way, the size of the P-channel MOS type transistor TR is reduced less than the size of the N-channel MOS type TR, and the CMOSIC characterized by a high speed and high integration density is obtained. |
