| 摘要 |
PURPOSE:To execute a conditional branch instruction in a high speed, by using a means, where information indicating that branch conditions are satisfied is stored, and two clock lines to skip fetch operations for rest words of the conditional branch instruction when branch is unnecessary. CONSTITUTION:When a branch instruction signal line 10 from an instruction decoder 4 becomes ''1'', the value of a program counter 1 is counted up to (N+2) by the signal of a clock signal line CLK2 and the ''0''-side output of a flip- flop 13, and the second word of a branch instruction is fetched in an instruction register 3. If branch conditions are not satisfied, the value of the program counter 1 is counted up to (N+3) by the signal of a clock signal line CLK1 and the ''0''-side output of the flip-flop 13, and the first word including the next operation code (OP code 2) is fetched from an ROM and is set to the instruction register 3. |
