| 摘要 |
PURPOSE:To process the transmission at speed being the division of the transmission speed by a number of parallel bits of a parallel signal by applying multiplication of a synchronizing signal without converting the parallel signal into a serial signal. CONSTITUTION:The titled circuit consists of a storage circuit 2 fetching and storing bits of the 2nd bit number in a prescribed bit location of each word of a number being the division of the 3rd bit number by the 1st bit number, a serial/parallel converter 3 converting the bit stored in the storage circuit 2 into a parallel signal comprising the 1st bit number and outputting the result, a frame pattern generator 4 generating sequentially bits constituting the frame pattern, a multiplexing circuit 5 taking the multiple location as the bit location of the word for the bit fetched and stored by the storage circuit 2, and a switch 6 receiving and outputting the output signal of the multiplex circuit 5 and switching it into an output signal of a serial/parallel converter for each prescribed word number. Thus, the simple circuit constitution with small power consumption and sufficient processing margin is obtained. |
