| 摘要 |
PURPOSE:To eliminate the need of an external circuit which switches memories from a user memory to a debugging memory at the time of a privileged interruption by using the timing signal of an active level as a memory bank switching signal for privileged interruption. CONSTITUTION:While a user program is executed, a privileged interruption inputting signal 2 is outputted from a privileged interruption factor producing circuit 16 and an effective signal is inputted to a privileged interruption inputting terminal 15 for evaluation. A single-chip microcomputer for evaluation 11 performs a privileged interruption process at appropriate timing after the user instruction being processed is completed. At the timing at which the operation of a CPU is switched to a privileged interruption processing state, an L-level privileged interruption outputting signal 3 is outputted from a terminal 14. The signal 3 is returned and again becomes inactive when the computer 11 executes an interruption returning process while the interruption process is performed. By using the signal 3 which becomes active while the computer 11 is in the privileged interruption processing state only, this signal is used as a memory bank switching signal. |
