发明名称 TIMING CIRCUIT
摘要 <p>PURPOSE:To prevent identification error from easily being caused by compensating so that a phase fluctuation characteristic of an output signal with respect to an input level of a limiter amplifier is made flat. CONSTITUTION:The circuit is provided with a peak detector 6 detecting the amplitude of an input signal of a limiter amplifier 5 and a variable phase shifter 7 varying the phase of a limiter amplifier output signal in response to the output of the detector 6. Then the peak of an output signal of a timing extraction filter 4 inputted to the limiter amplifier 5 is detected to control the phase of the clock signal of the limiter amplifier output by the variable phase shifter 7 in response to the output of the detector 6. Thus, the identification timing in an identification reproducing device 2 is kept optimizingly to identify and recover the reception signal. Thus, the identification error is hardly caused.</p>
申请公布号 JPH01222532(A) 申请公布日期 1989.09.05
申请号 JP19880048918 申请日期 1988.03.02
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SANADA TAKESHI
分类号 H04L7/027;H04L7/02 主分类号 H04L7/027
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