Circuit for serializing and deserializing digital data.

摘要

A circuit for serializing and deserializing digital data comprising at least two identical shift register circuits having common serial input ports and common parallel input and output ports. In a serial-to-parallel mode, one shift register alternately operates to receive serial data while the other shift register alternately operates to transmit a parallel word. In a parallel-to-serial mode of operation, one shift register alternately operates to receive a parallel word while the other shift register alternately operates to transmit serial data. The circuit further includes a automatic self-starting, word framing auto-correlating detector circuit for automatically starting and framing parallel words transfers upon detection of a unique "sync" pattern during the serial-to-parallel mode of operation. The detector circuit permits detection of the sync pattern even though some of the bits thereof are in error.