| 摘要 |
PURPOSE:To surely restart a processor to a momentary failure, by providing a monitor for restar processing on a common bus and transmitting a failure signal and a restart instruction via the common bus. CONSTITUTION:A common bus port 19 which outputs a CPU reset signal C1 on a common bus A, receives a restart instruction from the common bus A and outputs a failure circuit reset signal C2, and a failure detection circuit 14 which detects a failure in a processor are provided in the processor 1. On the other hand, a monitor circuit 2 connected to the common bus A has functions to receive the failure signal from the common bus, to perform restart processing predetermined for the said restart monitor timer and a counter and to output the restart instruction to the common bus A. The common bus A is used for data transmission normally, and in the fundamental transmission format, n data D0-Dn are transmitted succeeding to a data transmission discriminating command DT to distinguish the format from other transmission formats. |
