| 摘要 |
An apparatus for testing digital logic circuits without a computer and associated software employs a pseudorandom stream of input data to produce an unstructured output data stream which is analyzed by an efficient data collector and analyzer. Test signal generation is implemented by a pseudorandom number generator and a pseudorandom clock/reset generator while the resulting test data at the output terminals of the device under test is analyzed by a cycle redundancy code checker. Fault localization is realized, with selectable localization and manual probe modes and circuitry is provided for an efficient self-test mode. |
