发明名称 CLOCK GENERATING SYSTEM
摘要 <p>PURPOSE:To facilitate the generation of an optional clock signal with each cycle and to simplify the control of a memory, by using a holding circuit of an input signal and a control signal generating means. CONSTITUTION:A memory chip M incorporates a logical circuit and produces a memory controlling clock signal. In this case, an FF which holds an input signal is used along with a control signal generating means C which produces a write enable signal and a strobe signal by feeding the clock signal and the read/write signal among the input signals. The strobe signal is used to set the reading data in the reading mode.</p>
申请公布号 JPS57208688(A) 申请公布日期 1982.12.21
申请号 JP19810093471 申请日期 1981.06.17
申请人 FUJITSU KK 发明人 MORIOKA TSUNE
分类号 G11C11/41;G06F1/06;G11C7/22 主分类号 G11C11/41
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