发明名称 INTEGRATED CIRCUIT ARRANGEMENT IN MOS- TECHNOLOGY WITH FIELD EFFECT TRANSISTORS
摘要 <p>1 PHD. 79-011. During the fabrication of integrated circuits testing is necessary in order to enable faults to be located. For this purpose it is known to connect test points to specific points of the circuit, which during fabrication are accessible with a suitable designed scanner. Owing to the location of the test points smaller blocks are formed in comparison with the complete circuit arrangement. According to the invention transistor switched are included to provide isolation of selected input and output transistor blocks to allow separate testing as well as testing in combination.</p>
申请公布号 CA1138125(A) 申请公布日期 1982.12.21
申请号 CA19800345244 申请日期 1980.02.07
申请人 N.V. PHILIPS'GLOEILAMPENFABRIEKEN 发明人 HAPKE, FRIEDRICH
分类号 H01L21/822;G01R31/28;G06F11/267;H01L21/66;H01L21/82;H01L27/04;H01L29/78;(IPC1-7):01L21/66 主分类号 H01L21/822
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