发明名称 INPUT AND OUTPUT CONTROLLING SYSTEM
摘要 PURPOSE:To reduce useless processing of CPU which usually occur when the communication controller is connected to plural input output controller, by giving an autonomous retrial run function of the access to the communication controller and the file memory to the input output controller. CONSTITUTION:When an input output controller 3 receives a transfer signal from central controller 1, a common controlling section 34 makes an access request to a communication controller 5 and starts a timer 35 through a communication controller interface circuit 33. When the circuit 33 receives an answer from the controller 5, the circuit 33 sends a stop signal to the timer 35 and, at the same time, informs the control section 34 of the answer. When the stop signal does not come within a fixed time, the timer 35 gives a time-out signal to a counter 36 and informs the control section 34 of the time-out. When exceeds a fixed value, the counter 36 informs the control section of an overflow. The control section 34 makes a transfer operation against a normal answer and an access retrial run against time-out information and makes an abnormality completion report to the controller 1 against an overflow information. Therefore, useless processings of the controller caused by simultaneous access requests are reduced in number.
申请公布号 JPS57207922(A) 申请公布日期 1982.12.20
申请号 JP19810092961 申请日期 1981.06.18
申请人 NIPPON DENSHIN DENWA KOSHA;NIPPON DENKI KK;FUJITSU KK 发明人 HANABE KENICHI;OOMURA HIROYUKI;NAGAI MASAHIRO;NISHIDA MITSUO
分类号 G06F13/00;G06F13/12 主分类号 G06F13/00
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