发明名称 Instruction decoder for a pipeline processor.
摘要 <p>An information processing apparatus includes a decoder (3) for decoding an instruction, a general purpose register part (4) including a stack pointer and a plurality of general purpose registers, a special purpose register part (5) including a plurality of special purpose registers, and a processing part (6, 7, 13) coupled to the decoder, the general purpose register part and the special purpose register part for carrying out a predetermined process based on a decoded result from the decoder by selectively using a read out result of one of the general purpose register part and the special purpose register part. A decoding operation of the decoder, a read out operation of the general purpose register part and a read out operation of the special purpose register part are carried out in parallel.</p>
申请公布号 EP0416345(A2) 申请公布日期 1991.03.13
申请号 EP19900115715 申请日期 1990.08.16
申请人 FUJITSU LIMITED 发明人 SATO, TAIZO
分类号 G06F9/34;G06F9/30;G06F9/38;G06F9/42;G06F9/46;G06F9/48 主分类号 G06F9/34
代理机构 代理人
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