| 摘要 |
PURPOSE:To improve the efficiency of interruption processing of the titled processor, by commonly using hardware/firmware resources, such as register accumulator, etc., between plural microprogram executing levels which are different in priority. CONSTITUTION:When a controlling circuit 6 judges an occurrence of an interruption request of a level 2 which is higher in priority than the level 1 of another interruption being executed, the circuit 6 generates an instruction 40 and evacuates and plants the content of an address register 4 in a return address stack 5, and then, sets an execution start micro-instruction address of a microprogram executing level for the level 2 in the register 4. Then, the microprogram of the level 2 is executed. When an FF 12 is set, a firmware for level processing evacuates the contents of a register for working 7a, an accumulator, etc., in a high speed memory for working 11. If the FF 12 is set when the processing of the level 2 is completed, the planted contents are returned to the register 7a from the memory 11. |
