| 摘要 |
PURPOSE:To reduce the number of times of data transfer between a data processing device and a main memory by transferring the same data to other data processing units connected to a common bus simultaneously when the data is transferred from an aimed data processing unit to the main memory. CONSTITUTION:Data bus using request (DRQ) discriminating circuit 10 in a memory control unit 2 discriminates whether data bus is used (A) only between data processing units 4-6 and a main memory 3 or (B) between the data processing unit and the main memory 3 and between other data processing units on the basis of the previously set up information outputted from the processing unit 1. Data can be transferred by the two formats (A) and (B) and, in case of the format (B), the same data are transferred to other processing units simultaneously with the data transfer from an aimed processing unit to the main memory 3. When data processing unit processes a data by using the processed result of another processing unit, the number of times of data transfer is reduced and transfer efficiency is improved. |
