发明名称 MULTIPLIER/DIVIDER
摘要 PURPOSE:To shorten register length and calculation time by simultaneously calculating a product of 2 integers and the residue obtained by dividing the product by an integer. CONSTITUTION:Integers (x), (y), M are inputted to input terminals 101, 102, 103 respectively. A selective adder 105 adds the integer (x) to an output of a selective subtractor 107 only at the timing depending upon the integer (y) and, in other cases, the output of the selective subtractor 107 is outputted as it as. When the outputs of the selective adder 105 and a doubler 108 are an integer M or more, the selective subtractors 106, 107 find the difference between the integer M and each output respectively and, in other cases, output respective outputs as they are. The doubler 108 doubles the output of the selective subtractor 106.
申请公布号 JPS57206964(A) 申请公布日期 1982.12.18
申请号 JP19810092504 申请日期 1981.06.16
申请人 NIPPON DENKI KK 发明人 OKAMOTO EIJI;WATANABE KOUJIROU
分类号 G06F7/508;G06F7/52;G06F7/533;G06F7/64;G06F7/72 主分类号 G06F7/508
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