发明名称 CONTROL CIRCUIT OF PULL-UP RESISTANCE
摘要 PURPOSE:To reduce greatly the power consumption which is caused by the pull- up resistance, by separating the pull-up resistance when the input/output signal is set at a low level. CONSTITUTION:In the application mode of a power supply, a P-MOST3 is kept on until the power supply voltage VCC exceeds the threshold voltage of the P- MOST3. Thus an FF consisting of the NOR gates G1 and G2 is initialized. In other words, the points (a), (b) and (c) are set at a low level, a high level and a low level respectively. Thus an MOST2 is turned on to function as a pull-up resistance. Then the points (a), (b) and (c) are set at a high level, a low level and a high level respectively when the input of a terminal A is set at a low level. As a result, the P-MOST2 is turned off, and the pull-up resistance is cut off while the input is kept at a low level. When the input is set again at a high level, the point (c) is set at a low level and the terminal A is pulled up.
申请公布号 JPS57206131(A) 申请公布日期 1982.12.17
申请号 JP19810091804 申请日期 1981.06.15
申请人 FUJITSU KK 发明人 NAGAE YASUTAKA
分类号 H03K19/0175;H03K3/037;H03K3/356;H03K5/00;H03K17/16;H03K17/22;H03K19/00;H03K19/003 主分类号 H03K19/0175
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