发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To reduce leak current of the titled device provided with a substrate bias generating circuit by a method wherein a depletion type transistor is placed in an OFF state by a potential generated at the time of power ON with a polarity same as that of the substrate potential. CONSTITUTION:A substrate bias generating circuit 20 and a gate potential generating circuit 21 are provided in a MOS IC provided with an input gate protecting circuit consisting of a depletion type transistor. The substrate bias generating circuit 20 contains an oscillating circuit 22 whose output is supplied to the substrate 33 through a parallel circuit inculding a capacitor 29, diode 31, and a transistor 32. The gate potential generating circuit 21 is provided with an oscillating circuit 22' whose output is supplied to the gate of a transistor of the input gate protecting circuit through a capacitor 34 and transistor 36. When the power is made, a potential with a higher changing speed than the potential supplied to the substrate is supplied to the protecting circuit, thereby reducing transistor leak current.
申请公布号 JPS57206061(A) 申请公布日期 1982.12.17
申请号 JP19810090396 申请日期 1981.06.12
申请人 TOKYO SHIBAURA DENKI KK 发明人 IWAHASHI HIROSHI;ASANO MASAMICHI;KOBAYASHI ICHIROU
分类号 H01L27/04;G05F3/20;G11C11/407;H01L21/822;H01L29/78;H03K19/0944 主分类号 H01L27/04
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