| 摘要 |
PURPOSE:To reduce greatly the phase jitter and the slip of the reproduced carrier wave, by cutting off the output signal of a BPF when the S/N of the output signal is lowered and holding the phase of the output signal in case the S/N is high. CONSTITUTION:A 2<n> multiplying circuit 11 performs the 2<n> multiplication of input signal Ri and delivers the signal Ro to a BPF12. The BPF12 gives a band limitation to the noise component contained in the signal Ro and extracts the carrier 2<n> order higher harmonic component. A gate circut 21 decides the S/N of the output signal A of the BPF12 and limits the amplitude of the signal A when the S/N is higher than a prescribed level to supply the signal directly to a 2-division circuit 13. While the signal A is cut off when the S/N is lower than a certain level. Then the phase of the signal A is held in case the S/N is high, and a closed loop is formed together with the circuit 13 and a protecting signal generating circuit 22 to wait for the improvement of the S/N. The output Eo of the circuit 13 is applied to a 2<n-1>-division circuit 14 to obtain a reproduced carrier wave. In this circuit constitution, a carrier wave is obtained with no error by having the proper decision of S/N for the signal A. |
