发明名称 ASYNCHRONOUS OUTPUT SYSTEM OF DIGITAL DIFFERENTIAL ANALYZER
摘要 PURPOSE:To easily discriminate an error in fetching by adding a one-bit signal to output data of a specific address. CONSTITUTION:An address signal 2 from a digital differential analyzer DDA is decoded by a decoder 5 and if there is an address to be outputted, a gate 3 is opened by a decoding output 4 to store the output data 1 of the DDA in a buffer memory 7. In this case, while the gate 3 is opened for data on a specific address, connection with the memory 7 is made to store the data in the memory 7 together with an added one-bit signal. A CPU8 fetches data from the memory 7 one after another, but the range of data fetched at a time is made clear by finding the specific bit in the data, so that an error in fetching even if occurs is discriminated easily.
申请公布号 JPS57203138(A) 申请公布日期 1982.12.13
申请号 JP19810088181 申请日期 1981.06.10
申请人 HITACHI DENSHI KK 发明人 HIBINO KATSUHIKO;HAMAGUCHI YASUHIRO;SOGOU SABUROU
分类号 H03K19/177;G06F7/64 主分类号 H03K19/177
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