发明名称 ANALOG-TO-DIGITAL CONVERTER
摘要 PURPOSE:To deliver a correct signal with simple constitution, by defining a spot where a digital output is fixed before reading the output of a comparator and preventing the output of an erroneous digital signal produced by the difference of the circuit delay time. CONSTITUTION:A reference clock 1 is counted by a counter 31 of an A/D controller 3, and a clock 34 twice as much as the A/D clock 13 is delivered to be divided down to 1/2 by a counter 32. At the same time, the A/D start 12 synchronizing with the clear signal 36 and the clock 34 of the counters 31 and 32 is delivered by an MPX signal 2 that indicates a converting action through a counter 33. Then the clocks 13 and 34 are gated through an AND gate 35, and a holding clock 36 is delivered. The clock 36 is used for the working clocks of the digital output circuit of a converting circuit SAR14 and control circuits 141-150. Recording and fixing are carried out for SAR outputs 15-17 before the output 8 of a comparator 7 is written into the circuit SAR14. Thus an output of an erroneous digital signal which is delivered by the difference of the circuit delay time can be prevented.
申请公布号 JPS57203325(A) 申请公布日期 1982.12.13
申请号 JP19810088135 申请日期 1981.06.10
申请人 HITACHI SEISAKUSHO KK 发明人 UEKI YUKIYA
分类号 H03M1/38;H03M1/46;(IPC1-7):03K13/08 主分类号 H03M1/38
代理机构 代理人
主权项
地址