| 摘要 |
PURPOSE:To obtain high speed data transfer, by repeating the operation of sequential data reception and transmission for a vacant data buffer, in a plurality of controlling circuits. CONSTITUTION:The 1st data buffers 8 and 9 are divided into each two and respectively consist of 8A, 8B and 9A, 9B. Each one is arranged between a local bus 5 with less data capacity and a bus 4 to absorb the difference between the specifications of the buses. A control circuit 11 always receives a processing request if the processing request relating to a control circuit 12 is performed asynchronously. Control circuits 12-14 sequentially receive data as to a vacant data buffer and transmits the data with repetition. |
