| 摘要 |
A split load circuit (44) for driving a high speed load (72) and a low speed load (74) to the same logic state in response to one or more input signals. One input signal is provided to the gate terminals of pull-down transistors (48, 50, 52). The inverse of the input signal is provided to the gate terminals of pull-up transistors (64, 66). The high speed load (72) is connected between the pull-up transistor (64) and the pull-down transistor (50) and the low speed load (74) is connected between the pull-up transistor (66) and the pull-down transistor (52). When the input signal at the input node (46) is driven from one voltage state to another, the loads (72, 74) will be driven at different rates depending upon the capacitance and impedance of the load and the sizes of the pull-up transistors (64, 66) and the pull-down transistors (50, 52). The loads (72, 74) are driven independently such that much smaller pull-up and pull-down transistors can be utilized in place of a single pull-up and single pull-down transistor which would need to be fabricated much larger in order to meet the speed requirement of the high speed load (72) and to charge the high capacitance of the low speed load (74). Further, the power consumption is substantially reduced due to the reduced area of the transistors. |
