Structure and process for fabrication of stacked complementary MOS field effect transistor devices.

摘要

A method for fabricating a stacked complementary MOSFET device comprising the steps of: depositing a layer of phosphosilicate glass (58) on top of the gate electrode (56) of an N channel FET device (4) formed in the surface of a monocrystalline silicon substrate (50) having source (60) and drain (62) diffusions in said substrate on either side of said gate; depositing a layer of P-type polycrystalline silicon (65) over said phosphosilicate glass layer (58), extending over said source (60) and drain (62) diffusions and physically contacting a portion of the surface of said monocrystalline silicon substrate (50); heating said polycrystalline silicon layer (65) including said portion contacting said substrate (50) to a recrystallization temperature; cooling and recrystallizing said polycrystalline silicon layer (65) into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate (50); heating said phosphosilicate glass layer (58) so as to diffuse phosphorous atoms from said phosphosilicate glass layer upwardly into said silicon layer (65), forming an N-type region (78) which is juxtaposed with said gate electrode (56) and is self-aligned to said gate electrode. The structure of the complementary MOSFET device comprises an upper, P channel FET device (6) which is formed in said silicon layer (65), and which shares said gate electrode (56) with said N channel FET device (4).