发明名称 WIRE BONDING
摘要 <p>PURPOSE:To improve the efficiency of a bonding operation and to correct a bonding position with a small error even for the logical circuit substrate having a distorted circuit pattern by a method wherein, besides the semiconductor chip at both end parts of the logical circuit substrate, the position of bonding pad of the semiconductor chip located inside the above-mentioned two end parts are also detected. CONSTITUTION:Besides the detection of the position of specific bonding pad 11 of the semiconductor chip located at the starting end part of the logical circuit substrate 6, where a plurality of semiconductor chips 10 are provided, and also the detection of the position of the specific bonding pad (located at the position relatively same as the above-mentioned bonding pad), the position of the bonding pad same as the above-mentioned position at least one of the semiconductor chips is detected from the semiconductor chips located inside said two bonding pads. Then, the coordinate value of each of the above-mentioned positions detected by a visual device 8 is compared with the reference coordinate value of each designed position set in advance, the value of correction with which the error at each position becomes the minimum is worked out, the position of each bonding pad 11 on the above-mentioned substrate 6 is corrected using said value of correction, and a bonding operation is performed.</p>
申请公布号 JPS6376445(A) 申请公布日期 1988.04.06
申请号 JP19860219614 申请日期 1986.09.19
申请人 HITACHI LTD 发明人 SATO MITSUO;SUGIMOTO KOICHI
分类号 H01L21/60 主分类号 H01L21/60
代理机构 代理人
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