| 摘要 |
PURPOSE:To make gate speed at each output terminal faster and make each speed equal by a method wherein a plurality of collector regios and collector output terminals are laid next to base input terminals on the same line in a base region and a couple of such systems are laid parallel facting each other. CONSTITUTION:A p type base layer 2 of a horizontal type n-p-n transistor of a semiconductor integrated circuit device which composes an integrated injection logic circuit is so arranged to face an emitter p<+> layer 6 of the n-p-n transistor. Then collector regions 1a, 1b and 1c and output terminals 4a, 4b and 4c of a collector region 1 are formed on the base layer 2 in such a manner that those respective regions and terminals are laid parallel to the p<+> layer 6 with respective base input terminals 5a, 5b and 5c in between. |
