| 摘要 |
PURPOSE:To make the minimum gate propagation delay time characteristics at a plurality of output terminals smaller and equal by a method wherein collector regions, output terminals of the collector regions and a base input terminal are arranged for an injector region which is to be a current supply source. CONSTITUTION:A p type base layer 2 of a horizontal type n-p-n transistor of a semiconductor integrated circuit device which composes an integrated injection logic circuit is so arranged to face an emitter p<+> layer 6 of the n-p-n transistor. Then collector regions 1a, 1b and 1c and output terminals 4a, 4b and 4c of a collector region 1 are arranged on one line on the base layer 2 in such a manner that they are parallel to the p<+> layer 6. Then a base input terminal 5 is taken out from the outside of the respective output terminals 4a, 4b and 4c. For an injector which is to be a current supply source, at first a collector output terminal and then the base input terminal 5 are arranged. |
