| 摘要 |
PURPOSE:To obtain a high-speed and high-integration memory, by dividing an input/output line of storage information to plural sublines where storage information is processed independently of one another and controlling input/output storage information of sublines by the signal controlled by a decoder common to these sublines. CONSTITUTION:In a memory where a matrix is constituted with word lines W and data lines Dij to form a memory array, switches SWij controlled by an output control signal YC0 due to a Y decoder and a Y driver (YDEC) are provided, and data is transmitted and received between divided data lines of one another. Thus, a high-speed and high-output voltage read signal is obtained on a data line D from a memory cell MC by an X decoder and a word driver (XDEC), it is unnecessary to lay out the YDEC in the part of each switch conventionally, and it is sufficient if the common YDEC is provided, and the chip area is reduced. |
