| 摘要 |
PURPOSE:To prevent to attain a state where an interruption signal is inputted for a long time and the processing cannot be transferred to other processings, by detecting a period for a request signal and generating an error detection signal if the period is longer than a predetermined period. CONSTITUTION:When a counter 1 is reset at the initial state when an interruption signal S is inputted, a logic O is outputted from an output terminal Q2, AND condition of an AND circuit 3 is established, and a clock pulse from a clock oscillator 2 is inputted to the counter 1, and the counter 1 starts the count of the clock pulse. When the signal S is inputted for a very long time, the counter 1 sequentially counts the clock pulse and when the count value reaches 4, the logical value at the terminal Q2 goes to 1, and an error detection signal ES is outputted. Simultaneously, the AND condition of the circuit 3 is not established, and the counter 1 stops counting. When a failure is removed and the signal S is relinquished, the counter 1 is reset and prepares for the next interruption signal. |
