发明名称 CHATTERING PREVENTING CIRCUIT
摘要 PURPOSE:To prevent chattering with simple constitution by delaying a latch signal for setting an encoded output of an input signal from a key contact point to a flip-flop for a longer time than the chattering period of the key contact point. CONSTITUTION:To an encoder 1, contact point information (a) of information S0-Sn from a key contact point S is inputted, and its output (b) encoded in plural bits is applied to a flip-flop 6. To a gate circuit 3, an OR signal of the S0-Sn and the output from a clock generating circuit 2 are applied. The output (d) from the gate circuit 3 triggers a monostable multivibrator 4 and with the rise of its output (e) a multivibrator 5 sends a latch signal (f) that is delayed for the time longer than the chattering period to the flip-flop 6. With this process, a buffer gate 7 is capable of receiving information that is not affected by chattering.
申请公布号 JPS57197636(A) 申请公布日期 1982.12.03
申请号 JP19810082378 申请日期 1981.05.29
申请人 FUJITSU KK 发明人 HASHIMOTO HIROSHI
分类号 G06F3/02;H03M11/02 主分类号 G06F3/02
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