发明名称 MEMORY ACCESS CONTROLLING SYSTEM
摘要 PURPOSE:To increase the processing speed of an operating processing section, by providing a bank address storage means which registrates the block readout objective banks corresponding to all the banks and a readout bus busy register representing use or non-use of the readout data bus. CONSTITUTION:An instruction interpreting means (IDE) interpreting the instruction given from an operating processing section, a memory bank address storage means registrating the address of a block readout objective memory bank in advance, and a bus busy register (DBR) to which information representing the operating status of the memory bank is stored, are provided, and a write instruction to banks without duplicated operations can continuously be operated for block readout.
申请公布号 JPS57197662(A) 申请公布日期 1982.12.03
申请号 JP19810082339 申请日期 1981.05.29
申请人 NIPPON DENKI KK 发明人 SATOU TOSHIHIKO
分类号 G06F12/00;G06F12/06 主分类号 G06F12/00
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