MONITORING SYSTEM OF SIGNAL BUS

摘要

PURPOSE:To avoid disturbing a flow of a operation for an inter-processor communication program and furthermore to decrease the time required for the development of the program, by monitoring the information flowing to a communication signal bus between the processors and then displaying it to the outside independently. CONSTITUTION:The upper and lower values U and L of an address A to be monitored are written in the upper and lower limit address registers 13 and 14 to be held there. When the communication is carried out between the processors via a signal bus, the information of an address line is compared with the contents of the registers 13 and 14 through the comparators 15 and 16 respectively. Then the conditions to be within a range of U>A>=L is secured logically by an AND circuit 17, and a logic is secured between the output of the circuit 17 and the signal WRT of a writing control line through an AND circuit 18. Thus a writing request signal WRQ is produced for an FILO memory 19. The information WDT of the data line is written into the memory 19 when the signal WRQ is at the logic 1. The information written into the memory 19 is read in the order of the writing and displayed at a display device 11 in the form of the reading information RDT.