| 摘要 |
PURPOSE:To remarkably shorten a necessary time for processing, by providing a function part for forecasting the generation of carry from an adder, and executing the processing of normalization and round-off in accordance with a deciding output result value of the function part. CONSTITUTION:A data of the product derived by multiplication of a mantissa is registered to an accumulator register 11 and an extended register 12. At first, processing of normalization is executed, and whether bits 0-3 of the register 11 are zero or not is discriminated. In case of zero, subsequently, whether lower digits than a bit 4 of the register 11 are all ''1'' or not is decided by a carry generation forecasting circuit 15 in accordance with whether an output signal CLHAD of the circuit 15 is true or false, and only when the signal CLHAD is false, the registers 11 and 12 are left bit-shifted, and the normalization is executed. Subsequently, in case of round-off, addition by which a bit ''0'' of the register 12 is set as a carry-in (CI) input is executed. In this way, the processing sequence is simplified, the processing is executed at a high speed, and also operation of the exponential part is simplified. |
