| 摘要 |
<p>PURPOSE:To reduce a through-current, by providing a delay means for an input signal, in a series circuit consisting of MISFETs receiving the input signal and a signal phase-inverting the input signal. CONSTITUTION:A push-pull circuit PC is provided with two enhancement depletion type inverters and a push-pull output circuit consisting of enhancement type MISFETs E3 and E4 and acts as a prestage circuit of a bootstrap circuit BC. A delay means consisting of a resistor R1 and capacitors Cs1 and Cs2 is provided between the output of an MISFETE1 and the gate of an MISFETE4, and the delay characteristics are set so that they are coincident with those of the inverter consisting of the MISFET E2 and a D2. Thus, since the MISFETs E3 and E4 are not simultaneously turned on, the power consumption can be decreased.</p> |
