| 摘要 |
PURPOSE:To facilitate the program designing of the sequence, by using a memory device which stores the data common to the program and another memory device which is proper to the sequence process. CONSTITUTION:The terminal number which is presently under service is decided by a counter 3. The counter 3 is driven by a time division signal 8. Thus each terminal receives a periodical control. The changing time of the counter 3 is decided by a CPU9. A memory 1 which stores the data common with a program is distinguished from a memory 2 which stores the information for the purpose proper to the sequence process by the bit. This bit is provided to the format of address buses 4-6. Then the bit is designated to distinguish the data type of the format from the memories 1 and 2, and an access is given to the memory 2. As a result, the designing is facilitated for the program of the sequence to facilitate an easy debug. |
