发明名称 TIMING CONTROLLING CIRCUIT
摘要 PURPOSE:To simplify a circuit and to make the entire circuit of a control system compact, by constituting the circuit with one delay element, one flip-flop and several logical gates. CONSTITUTION:An FF31 is set with the 1st control signal, that is, MOTOR- START signal and reset with the 2nd control signal, that is, the MOTOR-STOP signal. An exclusive logical sum circuit 32 takes a signal delaying and inverting an output signal from a terminal Q of the FF31 at a delay element 33 as an input signal. The 1st NAND logical operation circuit 35 takes a signal obtained from the output signal from the terminal Q of the FF31 through delay and inversion as one input and the output signal from the circuit 32 as another input. In the 2nd NAND logical operating circuit 37, a signal obtained from the output signal at the terminal Q of the FF31 is taken as one input and the output signal of the circuit 32 is taken as another input.
申请公布号 JPS57196616(A) 申请公布日期 1982.12.02
申请号 JP19810080117 申请日期 1981.05.28
申请人 TOKYO SHIBAURA DENKI KK 发明人 MATSUMOTO SEIJIROU
分类号 H02P3/12;H03K3/64 主分类号 H02P3/12
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