| 摘要 |
PURPOSE:To prevent the occurrence of a malfunctions of a microcomputer by checking successively the instruction codes through a command memory before these codes are fetched by a CPU. CONSTITUTION:An instruction code which is read out of a memory 2 onto a data bus 10 in the instruction code fetching cycle of a CPU 1 is latched by a latch circuit 12 before an instruction code fetching state is set by a timing circuit 14. Then the latch output is given to the command memory of a next stage in the form of a read address. The command memory stores previously coincidence signals at each address position corresponding to each instruction code proper to the CPU 1. Then an error occurrence detecting signal is delivered from an output circuit as long as no coincidence is obtained between the instruction code received from the circuit 12 and the instruction code proper to the CPU 1. Therefore the CPU 1 can detect the presence or absence of influence of the disturbance noises, etc., and can take a measure to meet the interruption processing, etc. |
