| 摘要 |
PURPOSE:To prevent a latchup phenomenon by providing other conductivity type isolation layer which passes one conductivity type layer between a p- channel MOSFET and a C-channel MOSFET of CMOS unit. CONSTITUTION:After an n<+> type buried layer 2 is provided partly on a p-type Si substrate 1, an n<-> type epitaxial layer 3 is grown on the substrate 1. When a bipolar unit is separated by a p<+> type diffused layer 4, a p<+> type diffused layer 41 which arrives at the substrate 1 is formed between regions formed at an n-channel MOSFET and a p-channel MOSFET of a CMOS unit, and a p<-> type well layer 5 is formed by ion implanting to an n-channel MOSFET. Then, a p-type base layer 6, an n<+> type emitter layer 7 and an n<+> type collector electrode layer 8 are provided on the bipolar unit, an n<+> type source/drain diffused layer 9 is formed in the layer 5, and a p<+> type source/drain diffused layer 10 is formed in the layer 3. Further, a base electrode 12, an emitter electrode 13 and a collector electrode 14 are provided in an n-p-n transistor 21, a gate electrode 15 is provided on an oxide film 11 between the source and the drain, and electrodes 16, 17 are provided at the source/drain 9, 10. Thus, a latchup due to a thyristor effect can be prevented. |
