| 摘要 |
PURPOSE:To obtain a PLL lock detecting signal from a detecting circuit, by providing a circuit for detecting that an output pulse of a phase detecting circuit is in a continuous locked state in a pulse train sampled by a prescribed timing signal. CONSTITUTION:A programmable counter 2 applies a 1/N frequency-divided output to an input terminal D of a D-type flip-flop (FF) 3. From an output Q of the DFF 3, an inverted Fi which has pulse width corresponding to one period of an input signal FIN and has been frequency-divided into 1/N is formed, is used as an N-value preset gate pulse, also is inverted by an inverter INV, and is applied to one input Fi of a phase detecting circuit 1. To the other input of the phase detecting circuit 1, reference frequency REF is applied, and its outputs PD1, PD2 are applied to the gates of an n-MISFETQ2 and a p-MISFETQ1, respectively. A phase detecting output obtained in output circuits of Q2 and Q1 is converted to DC voltage by a filter 6, is sent to a VCO 7, and an output of the VCO 7 becomes a local oscillating signal together with the FIN. |
