发明名称 LEVEL DETECTING CIRCUIT
摘要 PURPOSE:To reduce the dispersion in detecting efficiency and to obtain a detected output with high accuracy, by applying a prescribed bias to the base of an input transistor (TR) in Darlington connection and input signals of phase opposite to each other to emitters of the output stage TRs respectively. CONSTITUTION:An input signal Vi is inputted to a 3-stage IF amplifier limiter and amplified through amplifiers 1st Amp-3rd Amp, and an IF output signal V0 is inputted to an FM detecting circuit FMDET. Level detecting circuits BTE1- BET3 connected to the amplifiers 1st Amp-3rd Amp are provided with two sets of TRs Q1 and Q2, and Q3 and Q4 in Darlington connection, a prescribed bias voltage is applied to the base of the TRs Q1 and Q3 at the input side and the emitters of the TRs Q2 and Q4 at the output side are connected in common. Input signals of opposite phase are applied to the emitter of the TRs Q1 and Q3 and the base of the TRs Q2 and Q4 via capacitors C1 and C2 and a detected signal is outputted from the collector of the TRs Q1-Q4 or the emitter of the TRs Q2 and Q4 in common connection.
申请公布号 JPS57192141(A) 申请公布日期 1982.11.26
申请号 JP19810076547 申请日期 1981.05.22
申请人 HITACHI SEISAKUSHO KK 发明人 IENAKA MASANORI
分类号 H04B1/16;H03J1/02;H03J3/14 主分类号 H04B1/16
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