| 摘要 |
PURPOSE:To increase the logical amplitude of a circuit through the reduction of effect of a voltage drop due to on-resistance, by connecting a plurality of source and drain of FETs mutually, using the FETs as driving elements, and connecting a current saturation type element using as a load to the drain side. CONSTITUTION:Sources and drains of n sets of normally off-type FETs 21 and 22 are connected mutually, and the sources are grounded and a normally on-type FET23 is connected to the drains, which is used as a load, to constitute a positive logic multiinput NAND gate circuit. The gates of the FETs 21 and 22 of this gate circuit are used as input termials 25 and 26, the drain is used as an output terminal 27, and the FETs 21 and 22 are used as driving elements. A DC power supply 24 is connected to the FETs 21 and 22 via the FET23 to set the saturation current of the FET23 so that it is smaller than n times the saturation current of the FETs 21 and 22 and larger than (n-1) times. The potential at the terminal 27 is made close to the ground potential when n-sets of the FETs 21 and 22 are turned on to reduce the effect of the voltage drop due to on-resistance. |
