发明名称 CONTINUOUS TRANSMITTING AND RECEIVING SYSTEM FOR BLOCK SIGNAL
摘要 PURPOSE:To reduce the load of the software and to allow continuous transfer of data, by providing the hardware consisting of a first-in and first-out register and a control circuit for a transmission and reception controlling circuit. CONSTITUTION:A first-in and first-out FiFo register 5 and a control circuit 6 are provided between transmission and reception controlling circuits 2 and 2' of a high level data link controlling means HDLC and a bus line BUS connected to a processor 1. One frame control information transferred from the processor 1 is transferred to the register 5 based on the control of a direct memory access controller DMAC7. Next, a data is read out from the register 5 with the control circuit 6 and the data is transferred to the control circuit by each one byte to continuously transfer data while reducing the load of the software. Similarly, the data from the control circuit 2' is continuously inputted to the processor 1.
申请公布号 JPS57192154(A) 申请公布日期 1982.11.26
申请号 JP19810077000 申请日期 1981.05.21
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA 发明人 NOJIMA SATOSHI;SHINRAI TAKASHI;YATSUHOSHI AKIMASA;TAKAHASHI TATSUROU;AOYAMA TOMONORI;UEDA HIROMI
分类号 H04L29/10;G06F13/00;G06F13/28 主分类号 H04L29/10
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