发明名称 FAILURE DETECTING METHOD FOR LOGICAL CIRCUIT
摘要 PURPOSE:To monitor a failure in a counter circuit and a logical circuit with very high probability, by monitoring a counting output signal of the counter circuit and the operation of the logical circuit with a monitor circuit. CONSTITUTION:A monitor circuit 4 inputs a count output signal D of a counter circuit 3 and discriminates that the operation of the circuit 3, a timer circuit 2 and a logical circuit 1 is correct if the count value (i) is within a prescribed range. Next, the circuit 4 executes increment of the circuit 3 by a number subtracting the count value (i) from the count up value (n) of the circuit 3 and checks if the counting output signal D from the circuit 3 is n. If not n, the circuit 4 judges it as a failure in the circuit 3 and compulsively outputs external output information I of an output circuit 5 to predetermined state. If the counting value (i) of the circuit 3 is not within the prescribed range, it is judged as a failure in the circuit 1, the information I is compulsively outputted to the predetermined state and the circuit is not started.
申请公布号 JPS57192132(A) 申请公布日期 1982.11.26
申请号 JP19810075760 申请日期 1981.05.21
申请人 NIPPON KOKUYU TETSUDO 发明人 OONO YOUJI;KAKUYAMA YOSHIHIRO
分类号 G06F11/30;G01R31/317;H03K19/00;H03K21/40 主分类号 G06F11/30
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