| 摘要 |
PROBLEM TO BE SOLVED: To reduce the size of terminal equipment and power consumption by avoiding the use of a high-speed clock signal at all the time by adopting a DSP-CPU connecting chip and adopting respectively suitable clock frequencies at the time of digital signal processing, equipment control and base station switching or at the time of soundless voices. SOLUTION: A DSP-CPU integrated chip 301 is used for housing a DSP core 423 and a CPU core 321 while sharing an instruction decoder 322 and for housing a clock signal generating circuit 313 together. To the DSP core 324 and the CPU core 321, an internal clock signal 113 at high speed in the case of digital signal processing to operate both the cores and at low speed in the case of following equipment control to use only the CPU core 321 is supplied from the generating circuit 313. Time dividing operation for alternately repeating this operation is adopted, the internal clock signals 113 at plural optimum frequencies are supplied, and the state of consuming no power at the time of base station switching or the like can be provided. Thus, the number of IC chips and power consumption can be reduced. |
