| 摘要 |
An algorithmic pattern generator produces an output data value during each cycle of a clock signal. The pattern generator includes an addressable instruction memory reading out an instruction during each clock signal cycle. A memory controller normally increments the instruction memory's address during each clock signal cycle, but may jump to another address N+1 clock signal cycles after receiving a CALL, RETURN, REPEAT or BRANCH command from an instruction processor. The instruction processor normally executes the instruction read out of the instruction memory during each clock signal cycle and provides a data field included in the executed instruction as the pattern generator's output data. Other fields of the instruction reference a command the instruction processor sends to the memory controller. Since the memory controller requires N+1 clock signal cycles to respond to a command, it continues to increment the instruction memory address for N clock signal cycles after receiving the command before it actually performs an address jump. Instead of the N instructions read out of instruction memory during the N clock signal cycles after sending a jump command, the instruction processor executes an appropriate set of N instructions pre-loaded into an auxiliary buffer memory. During the next clock signal pulse thereafter, when the memory controller has had time to make the address jump, the instruction processor resumes executing instructions read out of the instruction memory.
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